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Espressif Systems /ESP32-P4 /H264 /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DB_TMP_READY_INT_CLR)DB_TMP_READY_INT_CLR 0 (REC_READY_INT_CLR)REC_READY_INT_CLR 0 (FRAME_DONE_INT_CLR)FRAME_DONE_INT_CLR 0 (DMA_MOVE_2MB_LINE_DONE_INT_CLR)DMA_MOVE_2MB_LINE_DONE_INT_CLR

Description

Interrupt clear register

Fields

DB_TMP_READY_INT_CLR

Write 1 to clear H264_DB_TMP_READY_INT.
REC_READY_INT_CLR

Write 1 to clear H264_REC_READY_INT.
FRAME_DONE_INT_CLR

Write 1 to clear H264_FRAME_DONE_INT.
DMA_MOVE_2MB_LINE_DONE_INT_CLR

Clear bit: Write 1 to clear H264_DMA_MOVE_2MB_LINE_DONE_INT.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd